In very large-scale integrated circuits (VLSI), and even more so in ultra large-scale integrated (ULSI) circuits, the channel length of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) must be minimized. This allows a greater number of transistors to be fabricated on a single substrate and also provides for a faster transistor switching speed due to the shorter transit time of carriers moving between the source and the drain regions. One of the major difficulties with reducing the channel length is punch-through, in which the depletion layers from the source and drain regions contact one another, causing the potential barrier between the source and the drain to decrease. Punch-through results in significant leakage current, even when the transistor is in the off state.
The punch-through voltage (Vpt) of a device is defined as the drain-to-source voltage (Vds) at which the current from drain to source (Ids) reaches an unacceptable value with a gate-to-source voltage (Vgs) of zero. Punch-through must be suppressed in a device to the point where Vpt is larger than any possible Vds. One method for suppressing Vpt is to increase doping of the drain and source regions to decrease the depletion layer widths. Typically, this increased doping is used along with a threshold voltage adjust (Vt-adjust) implant. A Vt-adjust implant is a region of increased doping, e.g. boron in N-channel MOSFETs, phosphorous in P-channel MOSFETs. Other dopants for the Vt-adjust implant can include indium and boron difluoride (BF.sub.2). The Vt-adjust implant is typically implanted beneath the surface channel region to raise the dopant concentration beneath the surface channel region above the dopant concentration of the substrate. However, during the subsequent thermal annealing process, the dopant from this Vt-adjust implant may diffuse toward the surface and raise the dopant concentration in the channel, causing carrier mobility degradation due to increased impurity scattering.
Another method for suppressing Vpt is using "halo" implants. P-type dopants (in N-channel MOSFETs) are implanted under the lightly doped drain/source extensions (e.g., tip regions of the drain and source regions.) The implanted dopant raises the doping concentration only on the walls of the source and drain regions near the surface channel region. Thus, the channel length can be decreased without needing to use a substrate doped to a higher concentration. However, "halo" implants must be fabricated with great precision and may also result in an increase in the sidewall junction capacitance.
Accordingly, there is a need for an improved method of suppressing punch-through in an integrated circuit (IC). Further, there is a need for a method which allows for greater density of devices on the integrated circuit and improved efficiency of the IC. Even further still, there is a need for a punch-through suppression process which is easier to perform than prior punch-through suppression methods.